Table 22.36 Peripheral Module Signal Timing (3) - Hitachi SH7750 Hardware Manual

Table 22.36 Peripheral Module Signal Timing (3)

Module Item Symbol
TMU, Timer clock t
RTC
pulse width
(high)
Timer clock t
pulse width
(low)
Timer clock t
rise time
Timer clock t
fall time
Oscillation t
settling time
SCI Input clock t
cycle (asyn-
chronous)
Input clock t
cycle (syn-
chronous)
Input clock t
pulse width
Input clock t
rise time
Input clock t
fall time
Transfer data t
delay time
t
Receive data
setup time
(synchronous)
Receive data t
hold time
(synchronous)
I/O Output data t
ports delay time
Input data t
setup time
Input data t
hold time
Rev. 6.0, 07/02, page 928 of 986
HD6417750
F167
HD6417750 HD6417750
VF128 F167I
* 2
Min Max Min
4 — 4
TCLKWH
4 — 4
TCLKWL
— 0.8 —
TCLKr
— 0.8 —
TCLKf
— 3 —
ROSC
4 — 4
Scyc
6 — 6
Scyc
0.4 0.6 0.4
SCKW
— 0.8 —
SCKr
— 0.8 —
SCKf
1.3 10 1.3
TXD
16 — 16
RXS
16 — 16
RXH
0.5 10 0.5
PORTD
3.5 — 3.5
PORTS
1.5 — 1.5
PORTH
HD6417750
BP200M
* 3 * 4
Max Min Max Unit
Pcyc *
— 4 —
Pcyc *
— 4 —
Pcyc *
0.8 — 0.8
Pcyc *
0.8 — 0.8
3 — 3 s
Pcyc *
— 4 —
Pcyc *
— 6 —
0.6 0.4 0.6 t
Scyc
Pcyc *
0.8 — 0.8
Pcyc *
0.8 — 0.8
8 1.2 6 ns
— 16 — ns
— 16 — ns
8 0.5 6 ns
— 3 — ns
— 1.5 — ns
Figure
1
22.61
1
22.61
1
22.61
1
22.61
22.62
1
22.63
1
22.63
22.63
1
22.63
1
22.63
22.64
22.64
22.64
22.65
22.65
22.65