Hitachi SH7750 Hardware Manual page 461

1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g.
1024 cycles/128 ms).
2. When a transition is made to self-refreshing:
a. Provide an interrupt handler to restore the refresh counter count value to the optimum
value for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow
interrupt is generated.
b. Re-set the refresh counter count cycle to the requested short cycle (e.g. 1024 cycles/16
ms), set refresh controller overflow interruption, and clear the refresh controller's
refresh count register (RFCR) to 0.
c. Set self-refresh mode.
By using this procedure, the refreshing immediately following a self-refresh will be performed
in a short cycle, and when adequate refreshing ends, an interrupt is generated and the setting
can be restored to the original refresh cycle.
CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case
of a manual reset.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the
case of a manual reset.
When the bus has been released in response to a bus arbitration request, or when a transition is
made to standby mode, signals generally become high-impedance, but whether the RAS and
CAS signals become high-impedance or continue to be output can be controlled by the
HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.
As the DRAM CAS signal is multiplexed with WEn for normal memory (SRAM, etc.), access
to memory that uses the WEn signals must be disabled during self-refreshing.
• Relationship between Refresh Requests and Bus Cycle Requests
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus
cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as
a cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution
is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a
refresh is waiting to be executed, so that a new refresh request is generated, the previous
refresh request is eliminated. In order for refreshing to be performed normally, care must be
taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh
interval. When a refresh request is generated, the BACK pin is negated (driven high).
Therefore, normal refreshing can be performed by having the BACK pin monitored by a bus
Rev. 6.0, 07/02, page 411 of 986