Hitachi SH7750 Hardware Manual page 20

Section
Appendix F Synchronous
DRAM Address
Multiplexing Tables
Appendix H Power-On and
Power-Off Procedures
Appendix I Product Code
Lineup
Rev. 6.0, 07/02, page xx of I
Page Item
972, 973 (19) BUS 32
(128M: 4M × 8b × 4) × 4
(SH7750S and SH7750R
only)
(20) BUS 32
(256M: 4M × 16b × 4) × 2
(SH7750S and SH7750R
only)
977 to
979
980 Table I.1 SH7750 Series
Product Code Lineup
Description
SH7750R added
Newly added
SH7750R added