Hitachi SH7750 Hardware Manual page 33

21.1.2 Block Diagram..................................................................................................... 799
21.1.3 Pin Configuration................................................................................................. 801
21.1.4 Register Configuration......................................................................................... 802
21.2 Register Descriptions ........................................................................................................ 803
21.2.1 Instruction Register (SDIR) ................................................................................. 803
21.2.2 Data Register (SDDR) ......................................................................................... 805
21.2.3 Bypass Register (SDBPR) ................................................................................... 805
21.2.4 Interrupt Source Register (SDINT) (SH7750R Only).......................................... 806
21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) .......................................... 806
21.3 Operation .......................................................................................................................... 810
21.3.1 TAP Control......................................................................................................... 810
21.3.2 H-UDI Reset ........................................................................................................ 811
21.3.3 H-UDI Interrupt ................................................................................................... 811
21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) 812
21.4 Usage Notes ...................................................................................................................... 812
Section 22 Electrical Characteristics
22.1 Absolute Maximum Ratings ............................................................................................. 813
22.2 DC Characteristics ............................................................................................................ 814
22.3 AC Characteristics ............................................................................................................ 842
22.3.1 Clock and Control Signal Timing ........................................................................ 844
22.3.2 Control Signal Timing ......................................................................................... 868
22.3.3 Bus Timing .......................................................................................................... 871
22.3.4 Peripheral Module Signal Timing........................................................................ 924
22.3.5 AC Characteristic Test Conditions ...................................................................... 934
22.3.6 Delay Time Variation Due to Load Capacitance ................................................. 935
Appendix A Address List
Appendix B Package Dimensions
Appendix C Mode Pin Settings
Appendix D CKIO2ENB Pin Configuration
Appendix E Pin Functions
E.1 Pin States........................................................................................................................... 951
E.2 Handling of Unused Pins .................................................................................................. 954
Appendix F Synchronous DRAM Address Multiplexing Tables
Appendix G Prefetching of Instructions and its Side Effects
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