Hitachi SH7750 Hardware Manual page 679

Start
1
bit
Serial
0 D0
data
TDRE
TEND
TXI interrupt
request
Data written to SCTDR1
and TDRE flag cleared to
0 by TXI interrupt handler
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Data Parity Stop
bit bit
D1 D7 0/1 1
TXI interrupt
request
One frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Start Data
bit
0 D0 D1 D7
Rev. 6.0, 07/02, page 629 of 986
Parity Stop
1
bit bit
Idle state
0/1 1
(mark state)
TEI interrupt
request