General Registers - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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General Registers

Figure 2.3 shows the relationship between the processor modes and general registers. The SH7750

Series has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–

R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–

R15 in one processor mode. The SH7750 Series has two processor modes, user mode and

privileged mode, in which R0–R7 are assigned as shown below.

• R0_BANK0–R7_BANK0

In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0.

In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when

• R0_BANK1–R7_BANK1

In user mode, R0_BANK1–R7_BANK1 cannot be accessed.

In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1.

Rev. 6.0, 07/02, page 45 of 986

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