Hitachi SH7750 Hardware Manual page 433

Area 2: For area 2, external address bits A28 to A26 are 010.
SRAM, MPX, DRAM, and synchronous DRAM can be set to this area.
When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1
and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should
be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM
interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is
connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see
Memory Bus Width in section 13.1.5.
When area 2 is accessed, the CS2 signal is asserted.
When SRAM interface is set, the RD signal, which can be used as OE, and write control signals
WE0 to WE7, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3
register.
When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte
control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. RAS, CAS,
and data timing control, and address multiplexing control, can be set using the MCR register.
When DRAM is connected, the RAS2 signal, CAS4 to CAS7 signals, and RD/WR signal are
asserted, and address multiplexing is performed. RAS2, CAS, and data timing control, and address
multiplexing control, can be set using the MCR register.
Area 3: For area 3, external address bits A28 to A26 are 011.
SRAM, MPX, DRAM, and synchronous DRAM can be set to this area.
When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A3SZ1
and A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should
be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16,
32, or 64 bits can be selected with the SZ bits in the MCR register. When synchronous DRAM
interface is set, select 32 or 64 bits with the SZ bits in MCR. For details, see Memory Bus Width
in section 13.1.5.
When area 3 is accessed, the CS3 signal is asserted.
Rev. 6.0, 07/02, page 383 of 986