Hitachi SH7750 Hardware Manual page 247

19. LDC.L to SR: 4 issue cycles
I
D
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
D
I
21. STC.L from SGR: 3 issue cycles
D
I
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
D
I
23. STC.L from SGR: 3 issue cycles
D
I
24. LDS to PR, JSR, BSRF: 2 issue cycles
I
D
25. LDS.L to PR: 2 issue cycles
I
D
26. STS from PR: 2 issue cycles
D
I
27. STS.L from PR: 2 issue cycles
D
I
28. CLRMAC, LDS to MACH/L: 1 issue cycle
D
I
29. LDS.L to MACH/L: 1 issue cycle
D
I
30. STS from MACH/L: 1 issue cycle
D
I
Figure 8.2 Instruction Execution Patterns (cont)
EX MA
S
D
SX
D
SX
D
SX S
NA
D
SX
NA
SX S
NA
D
SX
NA
D SX
SX S
NA
D
SX
MA
SX S
NA
D
SX
NA
SX
D
EX NA
S
SX
D
SX
EX MA
S
SX
D
SX
SX S
NA
D
SX
NA
SX S
NA
D
SX
MA
EX S
NA
F1
F1
EX S
MA
F1
F1
EX S
NA
SX
S
S
NA S
S
S
MA S
S
S
F2 FS
F2 FS
Rev. 6.0, 07/02, page 197 of 986