Configuration Of The Dmac (Sh7750R); Block Diagram Of The Dmac - Hitachi SH7750 Hardware Manual

14.6

Configuration of the DMAC (SH7750R)

14.6.1

Block Diagram of the DMAC

Figure 14.53 is a block diagram of the DMAC in the SH7750R.
On-chip
peripheral
module
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
,
/
D[63:0]
External bus
ID[1:0]
DMAORn: DMAC operation register
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
n = 0 to 7
Rev. 6.0, 07/02, page 574 of 986
32B data
buffer
Bus state
controller
Figure 14.53 Block Diagram of the DMAC
DMAC module
Count control
Registr control
Activation
control
Request
priority
control
Bus
interface
8
Request
DTR command buffer
CH0
DBREQ
DDTMODE CH4
BAVL
DDTD
48 bits
id[2:0]
tdack
SARn
DARn
DMATCRn
CHCRn
DMAOR
queclr0–7
dmaqueclr0-7
SAR0, DAR0, DMATCR0,
CHCR0 only
DDT module
Request controller
CH1 CH2 CH3
CH5 CH6 CH7