Hitachi SH7750 Hardware Manual page 350

2. Channel 2 TCR bit configuration
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
3. TCR bit configuration for channels 3 and 4 (SH7750R only)
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are
always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in
channel 2 only, that indicates the occurrence of input capture.
Bit 9: ICPF
0
1
Note: * Writing 1 does not change the value.
Rev. 6.0, 07/02, page 300 of 986
15 14
— —
0 0
R R
7 6
ICPE1 ICPE0 UNIE
0 0
R/W R/W R/W
15 14
— —
0 0
R R
7 6
— — UNIE
0 0
R R R/W
Description
Input capture has not occurred
[Clearing condition]
When 0 is written to ICPF
Input capture has occurred
[Setting condition]
When input capture occurs*
13 12 11
— — —
0 0 0
R R R
5 4 3
CKEG1 CKEG0
0 0 0
R/W R/W
13 12 11
— — —
0 0 0
R R R
5 4 3
— —
0 0 0
R R
10 9
— ICPF
0 0
R R/W
2 1
TPSC2 TPSC1 TPSC0
0 0
R/W R/W
10 9
— —
0 0
R R
2 1
TPSC2 TPSC1 TPSC0
0 0
R/W R/W
(Initial value)
8
UNF
0
R/W
0
0
R/W
8
UNF
0
R/W
0
0
R/W