Figure 13.20 Dram Bus Cycle (Edo Mode, Rcd = 0, Anw = 0, Tpc = 1) - Hitachi SH7750 Hardware Manual

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EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only

while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also

provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the

CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. In the

SH7750, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access

using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM. When

EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure

13.20, and burst access in figure 13.21.

CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in

the MCR register.

(SA: IO ← memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)

Rev. 6.0, 07/02, page 403 of 986

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