Hitachi SH7750 Hardware Manual page 54

Table 1.1 SH7750 Series Features (cont)
Item
Clock pulse
generator (CPG)
Memory
management
unit (MMU)
Rev. 6.0, 07/02, page 4 of 986
Features
•
Choice of main clock:
 SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL
 SH7750R: 1, 6, or 12 times EXTAL
•
Clock modes:
 CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
 Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
 Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
Note: Maximum frequency varies with models.
•
Power-down modes
 Sleep mode
 Standby mode
 Module standby function
•
Single-channel watchdog timer
•
4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
•
Single virtual mode and multiple virtual memory mode
•
Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
•
4-entry fully-associative TLB for instructions
•
64-entry fully-associative TLB for instructions and operands
•
Supports software-controlled replacement and random-counter
replacement algorithm
•
TLB contents can be accessed directly by address mapping