(Tras[2:0] = 000, Trc[2:0] = 001) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Hide thumbs Also See for SH7750:

Table of Contents

(SA: IO ← memory)

(SA: IO → memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh

Rev. 6.0, 07/02, page 912 of 986

(TRAS[2:0] = 000, TRC[2:0] = 001)

Table of Contents

Sh7750r Sh7750s