Register Descriptions; Interrupt Priority Registers A To D (Ipra-Iprd) - Hitachi SH7750 Hardware Manual

H-UDI: Hitachi use debug interface
GPIOI: I/O port interrupt
DMTE0–DMTE7: DMAC transfer end interrupts
DMAE: DMAC address error interrupt
*1 Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the
SH7750, the initial values cannot be changed.
*2 SH7750R only
19.3

Register Descriptions

19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized
to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit: 15
Initial value: 0
R/W: R/W
Bit: 7
Initial value: 0
R/W: R/W
IPRD (SH7750S and SH7750R only)
Bit: 15
Initial value: 1
R/W: R/W
Bit: 7
Initial value: 0
R/W: R/W
14 13
0 0
R/W R/W
6 5
0 0
R/W R/W
14 13
1 0
R/W R/W
6 5
1 1
R/W R/W
12 11
0 0
R/W R/W R/W
4 3
0 0
R/W R/W R/W
12 11
1 1
R/W R/W R/W
4 3
1 0
R/W R/W R/W
Rev. 6.0, 07/02, page 761 of 986
10 9
0 0
R/W R/W
2 1
0 0
R/W R/W
10 9
0 1
R/W R/W
2 1
1 0
R/W R/W
8
0
0
0
8
0
0
0