Table 14.5 Selecting On-Chip Peripheral Module Request Mode With Rs Bits - Hitachi SH7750 Hardware Manual

When DMA transfer is restarted, check whether a DMA transfer request is being held.
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to
a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in
table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit
(TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the
two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full
interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2).
When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty
interrupt), the transfer destination must be the SCI/SCIF's transmit data register
(SCTDR1/SCFTDR2).

Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits

RS3 RS2 RS1 RS0
1 0 0 0
1
1 0
1
1 0 0
1
1 0
TMU: Timer unit
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
Notes: 1. SCI/SCIF burst transfer setting is prohibited.
Rev. 6.0, 07/02, page 514 of 986
DMAC Transfer DMAC Transfer
Request Source Request Signal
SCI transmitter SCTDR1 (SCI
transmit-data-
empty transfer
request)
SCI receiver SCRDR1 (SCI
receive-data-full
transfer request)
SCIF transmitter SCFTDR2 (SCIF
transmit-data-
empty transfer
request)
SCIF receiver SCFRDR2 (SCIF
receive-data-full
transfer request)
TMU channel 2 Input capture
occurrence
TMU channel 2 Input capture
occurrence
TMU channel 2 Input capture
occurrence
Transfer Transfer
Source Destination Bus Mode
External* SCTDR1
SCRDR1 External*
External* SCFTDR2
SCFRDR2 External*
External* External*
External* On-chip
peripheral
On-chip External*
peripheral
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode