Hitachi SH7750 Hardware Manual page 573

Sh7750 series superh risc engine

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Figure 14.9 Example of DMA Transfer in Cycle Steal Mode

Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers

data continuously until the transfer end condition is satisfied. With DREQ low level detection in

external request mode, however, when DREQ is driven high the bus passes to another bus master

after the end of the DMAC transfer request that has already been accepted, even if the transfer end

condition has not been satisfied.

Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in

this example are single address mode and DREQ level detection (CHCRn.DS = 0, CHCRn.TM =

Figure 14.10 Example of DMA Transfer in Burst Mode

Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode

setting can also be made.

Relationship between DMA Transfer Type, Request Mode, and Bus Mode

Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the

Bus returned to CPU

Rev. 6.0, 07/02, page 523 of 986

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