Hitachi SH7750 Hardware Manual page 727

Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used
to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of
transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the
following table.
Bit 5: TTRG1 Bit 4: TTRG0
0 0
1
1 0
1
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals.
Bit 3: MCE
0
1
Note: * CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the
transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST
0
1
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
0
1
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Transmit Trigger Number
8 (8)
4 (12)
2 (14)
1 (15)
Description
Modem signals disabled*
Modem signals enabled
Description
Reset operation disabled*
Reset operation enabled
Description
Reset operation disabled*
Reset operation enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 6.0, 07/02, page 677 of 986