Clock-Stop Clear Register 00 (Clkstpclr00) (Sh7750R Only) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Hide thumbs Also See for SH7750:

Table of Contents

Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to

channels 3 and 4 of the timer unit (TMU).

Bit 1: CSTP1

Bit 0    Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt

controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and

Bit 0: CSTP0

Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)

The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the

corresponding bits of the CLKSTP00 register.

Initial value:

Initial value:

Bits 31 to 0    Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the

clock-stop setting. See section 9.2.5, Clock-Stop Register 00 (LKSTP00) (SH7750R only), for the

correspondence between the bits and the clocks that are stopped.

Bits 31 to 0

Peripheral clock is supplied to TMU channels 3 and 4

Peripheral clock supply to TMU channels 3 and 4 is stopped

INTC detects interrupts on channels 3 and 4 of the TMU

INTC does not detect interrupts on channels 3 and 4 of the TMU

Does not change the clock-stop setting for the corresponding clock

Clears the clock-stop setting for the corresponding clock

Rev. 6.0, 07/02, page 229 of 986

(Initial value)

Table of Contents

Sh7750r Sh7750s