Bus Control Register 4 (Bcr4) (Sh7750R Only); Figure 13.4 Example Of Rdy Sampling Timing At Which Bcr4 Is Set (Two Wait Cycles Are Inserted By Wcr2) - Hitachi SH7750 Hardware Manual

Bits 12 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0    Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is
used. The burst-length setting is only valid when the bus width is 32 bits.
Bit 0: SDBL
0
1
13.2.4

Bus Control Register 4 (BCR4) (SH7750R Only)

Bus control register 4 (BCR4) is a 32-bit readable/writable register that enables asynchronous
input to the pin corresponding to each bit.
BCR4 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than
when synchronous input is set (ASYNCn = 0)* (see figure 13.4)
The timings shown in this section and section 22, Electrical Characteristics, are all for the case
where synchronous input is set (ASYNCn = 0).
Note: * With the synchronous input setting, ensure that setup and hold times are observed.
CKIO
(BCR4.ASYNC0 = 0)
(BCR4.ASYNC0 = 1)
Figure 13.4 Example of RDY
Rev. 6.0, 07/02, page 338 of 986
Description
Burst length is 8
Burst length is 4
T1 Tw
RDY Sampling Timing at which BCR4 is Set RDY RDY
(Two Wait Cycles are Inserted by WCR2)
Tw Twe
(Initial value)
T2