Overview; Sh7750 Series (Sh7750, Sh7750S, Sh7750R) Features - Hitachi SH7750 Hardware Manual

1.1

SH7750 Series (SH7750, SH7750S, SH7750R) Features

The SH7750 Series (SH7750, SH7750S, SH7750R) is a 32-bit RISC (reduced instruction set
computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-
3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back
or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative
unified TLB (translation lookaside buffer). The SH7750 and SH7750S have an 8-kbyte instruction
cache and a 16-kbyte data cache. The SH7750R has a 16-kbyte instruction cache and a 32-kbyte
data cache.
The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM
and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be
reduced by almost 50% compared with 32-bit instructions.
The features of the SH7750 Series are summarized in table 1.1.
Table 1.1 SH7750 Series Features
Item
LSI
Section 1 Overview
Features
•
Operating frequency: 240 MHz *
3
128 MHz *
•
Performance
 432 MIPS (240 MHz), 360 MIPS (200 MHz), 300 MIPS (167 MHz),
240 MIPS (133 MHz), 230 MIPS (128 MHz)
 1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz),
1.2 GFLOPS (167 MHz), 0.9 GFLOPS (133 MHz, 128 MHz)
•
Superscalar architecture: Parallel execution of two instructions
•
Packages: 256-pin BGA, 208-pin QFP, 264-pin CSP *
•
External buses
 Separate 26-bit address and 64-bit data buses
 External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus
frequency
1
, 200 MHz, 167 MHz *
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2 3 2
* , 133 MHz *
,
2