Hitachi SH7750 Hardware Manual page 554

Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9:
RS3 RS2 RS1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Notes: *1 External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
*2 Dual address mode
*3 In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56]
(MD1, MD0 bits) specification for channel 0 only.
*4 In DDT mode:
[SH7750]
[SH7750S] An external request specification can be set for channels 0 to 3.
Rev. 6.0, 07/02, page 504 of 986
Bit 8:
RS0 Description
External request, dual address mode *
0
space → external address space)
1 Setting prohibited
0 External request, single address mode
External address space → external device *
1 External request, single address mode
External device → external address space *
Auto-request (external address space → external address
0
2
space) *
Auto-request (external address space → on-chip peripheral
1
2
module) *
Auto-request (on-chip peripheral module → external address
0
2
space) *
1 Setting prohibited
0 SCI transmit-data-empty interrupt transfer request
(external address space → SCTDR1) *
1 SCI receive-data-full interrupt transfer request
(SCRDR1 → external address space) *
0 SCIF transmit-data-empty interrupt transfer request
(external address space → SCFTDR2) *
1 SCIF receive-data-full interrupt transfer request
(SCFRDR2 → external address space) *
0 TMU channel 2 (input capture interrupt, external address space
→ external address space) *
1 TMU channel 2 (input capture interrupt, external address space
→ on-chip peripheral module) *
0 TMU channel 2 (input capture interrupt, on-chip peripheral
module → external address space) *
1 Setting prohibited
An external request specification should be set for channels 1 to 3. For
channel 0, only single address mode can be set with the DTR format.
1 4
*
(external address
1 3 4
* *
1 3 4
* *
2
2
2
2
2
2
2
(Initial value)