Hitachi SH7750 Hardware Manual page 366

Table 13.1 BSC Pins (cont)
Name Signals
WE6/CAS6/
Data enable 6
DQM6
WE7/CAS7/
Data enable 7
DQM7/REG
RDY
Ready
Area 0 MPX MD6/IOIS16
interface
specification/
16-bit I/O
Clock enable CKE
BREQ/
Bus release
BSACK
request
BACK/
Bus use
BSREQ
permission
MD3/CE2A *
Area 0 bus
width/PCMCIA
MD4/CE2B *
card select
MD5/RAS2 *
Endian switchover/
row address strobe
Master/slave MD7/TXD
switchover
DMAC0 DACK0
acknowledge
signal
DMAC1 DACK1
acknowledge
signal
Rev. 6.0, 07/02, page 316 of 986
I/O Description
O When setting synchronous DRAM interface:
selection signal for D55–D48
When setting DRAM interface: CAS signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
O When setting synchronous DRAM interface:
selection signal for D63–D56
When setting DRAM interface: CAS signal for
D63–D56
When setting PCMCIA interface: REG signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
I Wait state request signal
I In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
O Synchronous DRAM clock enable control signal
I Bus release request signal/bus acknowledge signal
O Bus use permission signal/bus request
1
In power-on reset *
I/O
specification signal
2
When setting PCMCIA interface: CE2A, CE2B
3
Endian specification in a power-on reset. *
I/O
RAS2 when DRAM is connected to area 2
Indicates master/slave status in a power-on reset. *
I/O
Serial interface TXD
O DMAC channel 0 data acknowledge
O DMAC channel 1 data acknowledge
4
: external space area 0 bus width
4
4