Hitachi SH7750 Hardware Manual page 48

Table 14.2 DMAC Pins in DDT Mode ................................................................................ 494
Table 14.3 DMAC Registers................................................................................................ 494
Table 14.4 Selecting External Request Mode with RS Bits................................................. 513
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits.................. 514
Table 14.6 Supported DMA Transfers................................................................................. 518
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode..... 524
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode ............. 525
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ................. 526
Table 14.10 Conditions for Transfer between External Memory and an External Device
with DACK, and Corresponding Register Settings............................................ 544
Table 14.11 DMAC Pins........................................................................................................ 575
Table 14.12 DMAC Pins in DDT Mode ................................................................................ 576
Table 14.13 Register Configuration....................................................................................... 577
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1) .................................. 584
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode ....................... 587
Function of BAVL ............................................................................................. 587
Table 14.16
Table 14.17 DTR Format for Clearing Request Queues........................................................ 588
Table 14.18 DMAC Interrupt-Request Codes ....................................................................... 589
Table 15.1 SCI Pins ............................................................................................................. 596
Table 15.2 SCI Registers ..................................................................................................... 596
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. 615
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode ............... 618
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) ....................................................................................... 619
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ............. 620
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)................ 620
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection.................................... 622
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection ..................... 622
Table 15.10 Serial Transfer Formats (Asynchronous Mode)................................................. 624
Table 15.11 Receive Error Conditions................................................................................... 632
Table 15.12 SCI Interrupt Sources......................................................................................... 651
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data ......................................... 652
Table 16.1 SCIF Pins ........................................................................................................... 660
Table 16.2 SCIF Registers ................................................................................................... 661
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection.................................... 685
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection.......................................... 686
Table 16.5 Serial Transmit/Receive Formats....................................................................... 687
Table 16.6 SCIF Interrupt Sources ...................................................................................... 697
Table 17.1 Smart Card Interface Pins .................................................................................. 705
Table 17.2 Smart Card Interface Registers .......................................................................... 705
Table 17.3 Smart Card Interface Register Settings .............................................................. 713
Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings................................ 715
Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) .. 716
Rev. 6.0, 07/02, page xlviii of I