Table 21.3 Configuration Of The Boundary Scan Register (3) - Hitachi SH7750 Hardware Manual

Table 21.3 Configuration of the Boundary Scan Register (3)

No. Pin Name
WE5/CAS5/DQM5
118
WE5/CAS5/DQM5
117
116 CKE
115 CKE
114 D7
113 D7
112 D7
111 D8
110 D8
109 D8
BREQ/BSACK
108
BACK/BSREQ
107
BACK/BSREQ
106
105 D6
104 D6
103 D6
102 D9
101 D9
100 D9
99 D5
98 D5
97 D5
96 D10
95 D10
94 D10
93 D4
92 D4
91 D4
90 D11
89 D11
88 D11
87 D3
86 D3
85 D3
84 D12
83 D12
82 D12
81 D2
80 D2
79 D2
Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Type No. Pin Name
CTL 78 D13
OUT 77 D13
CTL 76 D13
OUT 75 D1
IN 74 D1
CTL 73 D1
OUT 72 D14
IN 71 D14
CTL 70 D14
OUT 69 D0
IN 68 D0
CTL 67 D0
OUT 66 D15
IN 65 D15
CTL 64 D15
OUT 63 D39
IN 62 D39
CTL 61 D39
OUT 60 D40
IN 59 D40
CTL 58 D40
OUT 57 D38
IN 56 D38
CTL 55 D38
OUT 54 D41
IN 53 D41
CTL 52 D41
OUT 51 D37
IN 50 D37
CTL 49 D37
OUT 48 D42
IN 47 D42
CTL 46 D42
OUT 45 D36
IN 44 D36
CTL 43 D36
OUT 42 D43
IN 41 D43
CTL 40 D43
OUT 39 D35
Type No. Pin Name
IN 38 D35
CTL 37 D35
OUT 36 D44
IN 35 D44
CTL 34 D44
OUT 33 D34
IN 32 D34
CTL 31 D34
OUT 30 D45
IN 29 D45
CTL 28 D45
OUT 27 D33
IN 26 D33
CTL 25 D33
OUT 24 D46
IN 23 D46
CTL 22 D46
OUT 21 D32
IN 20 D32
CTL 19 D32
OUT 18 D47
IN 17 D47
CTL 16 D47
RD2
OUT 15
RD2
IN 14
BS
CTL 13
BS
OUT 12
IN 11 CS6
CTL 10 CS6
OUT 9 CS5
IN 8 CS5
CTL 7 CS4
OUT 6 CS4
IN 5 CS1
CTL 4 CS1
OUT 3 CS0
IN 2 CS0
RDY
CTL 1
OUT to TDO
IN
Rev. 6.0, 07/02, page 809 of 986
Type
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
IN