Hitachi SH7750 Hardware Manual page 979

Module Item Symbol
DREQn
DMAC t
setup time
DREQn
t
hold time
DRAKn t
delay time
INTC NMI pulse t
width (high)
NMI pulse t
width (low)
H-UDI Input clock t
cycle
Input clock t
pulse width
(high)
Input clock t
pulse width
(low)
Input clock t
rise time
Input clock t
fall time
ASEBRK
t
setup time
ASEBRK
t
hold time
TDI/TMS t
setup time
TDI/TMS t
hold time
t
TDO delay
time
ASE-PINBRK t
pulse width
Notes: *1 Pcyc: P clock cycles
*2 V = 3.0 to 3.6 V, V
DDQ
*3 V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167)
V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167I)
*4 V = 3.0 to 3.6 V, V
DDQ
HD6417750
F167
HD6417750 HD6417750
VF128 F167I
* 2
Min Max Min
3.5 — 3.5
DRQS
1.5 — 1.5
DRQH
1.0 10 1.0
DRAKD
5 — 5
NMIH
30 — 30
5 — 5
NMIL
30 — 30
50 — 50
TCKcyc
15 — 15
TCKH
15 — 15
TCKL
— 10 —
TCKr
— 10 —
TCKf
10 — 10
ASEBRKS
10 — 10
ASEBRKH
15 — 15
TDIS
15 — 15
TDIH
0 10 0
TDO
2 — 2
PINBRK
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –40 to +85°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
HD6417750
BP200M
* 3 * 4
Max Min Max Unit
— 3 — ns
— 1.5 — ns
8 1.0 6 ns
— 5 — t
cyc
— 30 — ns
— 5 — t
cyc
— 30 — ns
— 50 — ns
— 15 — ns
— 15 — ns
10 — 10 ns
10 — 10 ns
— 10 — t
cyc
— 10 — t
cyc
— 15 — ns
— 15 — ns
10 0 10 ns
Pcyc *
— 2 —
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
Rev. 6.0, 07/02, page 929 of 986
Figure
22.66
22.66
22.66
Normal or sleep mode
22.71
Standby mode
22.71
Normal or sleep mode
22.71
Standby mode
22.71
22.67
22.67
22.67
22.67
22.67
22.68
22.68
22.69
22.69
22.69
1
22.70