Pin Configuration; Register Configuration; Table 19.1 Intc Pins; Table 19.2 Intc Registers - Hitachi SH7750 Hardware Manual

19.1.3

Pin Configuration

Table 19.1 shows the INTC pin configuration.

Table 19.1 INTC Pins

Pin Name
Nonmaskable interrupt
input pin
Interrupt input pins
19.1.4

Register Configuration

The INTC has the registers shown in table 19.2.

Table 19.2 INTC Registers

Name Abbreviation
Interrupt control ICR
register
Interrupt priority IPRA
register A
Interrupt priority IPRB
register B
Interrupt priority IPRC
register C
Interrupt priority IPRD
3
register D *
Interrupt priority INTPRI00
level setting
4
register 00 *
Interrupt source INTREQ00
4
register 00 *
Interrupt mask INTMSK00
4
register 00 *
Interrupt mask INTMSKCLR00 R
4
clear register 00 *
Notes: *1 Initialized by a power-on reset or manual reset.
*2 H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
*3 SH7750S and SH7750R only
*4 SH7750R only
Abbreviation I/O
NMI Input
IRL3–IRL0
Input
Initial Value *
R/W
2
*
R/W
R/W H'0000
R/W H'0000
R/W H'0000
R/W H'DA74
R/W H'00000000
R H'00000000
R/W H'00000300
—
Function
Input of nonmaskable interrupt request
signal
Input of interrupt request signals
(maskable by I3–I0 in SR)
1
Area 7
P4 Address Address
H'FFD00000 H'1FD00000
H'FFD00004 H'1FD00004
H'FFD00008 H'1FD00008
H'FFD0000C H'1FD0000C
H'FFD00010 H'1FD00010
H'FE080000 H'1E080000
H'FE080020 H'1E080020
H'FE080040 H'1E080040
H'FE080060 H'1E080060
Rev. 6.0, 07/02, page 753 of 986
Access
Size
16
16
16
16
16
32
32
32
32