Figure 22.5 Power-On Oscillation Settling Time; Figure 22.6 Standby Return Oscillation Settling Time (Return By Reset) - Hitachi SH7750 Hardware Manual

Internal clock
VDD
SCK2
MD8, MD7,
MD2–MD0
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Standby
Internal
clock
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 operating
Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET
Rev. 6.0, 07/02, page 864 of 986
V min
DD
t
OSC1
t
OSCMD

Figure 22.5 Power-On Oscillation Settling Time

Stable oscillation
t
RESW
t
SCK2RH
t
MDRH
t
TRSTRH
t
RESW
t
OSC2
Stable oscillation
RESET) RESET RESET