Hitachi SH7750 Hardware Manual page 590

Figure 14.22 Single Address Mode/Burst Mode
DREQ (Level Detection)/32-Byte Block Transfer
DREQ DREQ
External Bus → → → → External Bus/DREQ
(Bus Width: 64 Bits, SDRAM: Row Hit Write)
Rev. 6.0, 07/02, page 540 of 986