Hitachi SH7750 Hardware Manual page 474

Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
CKIO
Bank
Precharge-sel H/L
c1
Address
RD/
DQMn
D63–D0
c1 c2 c3 c4
(read)
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.33 Burst Read Timing (RAS Down, Same Row Address)
Rev. 6.0, 07/02, page 424 of 986