Hitachi SH7750 Hardware Manual page 593

2. End of transfer when NMIF = 1 in DMAOR
If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on
all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is
passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address
register (SAR), DMA destination address register (DAR), and DMA transfer count register
(DMATCR) indicate the addresses for the DMA transfer to be performed next and the
remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after
NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1
from it. As in the case of AE being set to 1, acceptance of external requests is suspended while
NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer.
Acceptance of internal requests is also suspended, so when resuming transfer, the DMA
transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0
before the new setting is made.
3. End of transfer when DME = 0 in DMAOR
If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in
accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the
CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA
source address register (SAR), DMA destination address register (DAR), and DMA transfer
count register (DMATCR) indicate the addresses for the DMA transfer to be performed next
and the remaining number of transfers. When resuming transfer, DME must be set to 1.
Operation will then be resumed from the next transfer.
Rev. 6.0, 07/02, page 543 of 986