Hitachi SH7750 Hardware Manual page 6

Section
3.3.3 Virtual Address Space
3.3.4 On-Chip RAM Space
3.3.7 Address Space
Identifier (ASID)
4.1.1 Features
4.2 Register Descriptions
4.3.1 Configuration
4.3.6 RAM Mode
4.3.7 OC Index Mode
4.4.1 Configuration
4.6 Memory-Mapped Cache
Configuration (SH7750R)
4.7 Store Queues
4.7.3 Transfer to External
Memory
4.7.4 SQ Protection
4.7.5 Reading the SQs
(SH7750R Only)
4.7.6 SQ Usage Notes
5.2 Register Descriptions
5.4 Exception Types and
Priorities
Rev. 6.0, 07/02, page vi of I
Page Item
68, 69
69
70
95 Table 4.1 Cache Features
(SH7750, SH7750S)
95 Table 4.2 Cache Features
(SH7750R)
96 Table 4.3 Features of Store
Queues
97 Figure 4.1 Cache and Store
Queue Control Registers
97 (1) Cache Control Register
(CCR)
101 Figure 4.3 Configuration of
Operand Cache (SH7750R)
106 to
107
107
109
110 Figure 4.7 Configuration of
Instruction Cache (SH7750R)
116
122
122, 123
124
124
125
128
130 to Table 5.2 Exceptions
132
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figure 4.6, description
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