Hitachi SH7750 Hardware Manual page 65

Table 1.2 Pin Functions (cont)
Pin
No. No. Pin Name
BACK/
61 U3
BSREQ
BREQ/
62 V3
BSACK
63 W2 D8
64 Y2 D7
65 W3 CKE
66 V5 VDDQ
67 U5 VSSQ
WE5/CAS5/
68 Y3
DQM5
WE4/CAS4/
69 W4
DQM4
WE1/CAS1/
70 Y4
DQM1
WE0/CAS0/
71 W5
DQM0
72 Y5 A17
73 V6 VDDQ
74 U6 VSSQ
75 W6 A16
76 Y6 A15
77 V7 VDD
78 U7 VSS
79 W7 A14
80 Y7 A13
81 V8 VDDQ
82 U8 VSSQ
83 V4 NC
84 W8 A12
85 Y8 A11
86 W9 A10
I/O Function
O Bus
acknowledge/
bus request
I Bus
request/bus
acknowledge
I/O Data
I/O Data
O Clock output
enable
Power IO VDD (3.3 V)
Power IO GND (0 V)
O D47–D40
select signal
O D39–D32
select signal
O D15–D8 select
signal
O D7–D0 select
signal
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Power Internal VDD
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
Reset SRAM DRAM
WE5 CAS5
WE4 CAS4
WE1 CAS1
WE0 CAS0
Memory Interface
SDRAM PCMCIA MPX
CKE
DQM5
DQM4
WE1
DQM1
DQM0
Rev. 6.0, 07/02, page 15 of 986
A8
A7