Table 19.3 Irl3-Irl0 Pins And Interrupt Levels - Hitachi SH7750 Hardware Manual

Table 19.3 IRL3 IRL3 IRL3 IRL3–IRL0 IRL0 IRL0 IRL0 Pins and Interrupt Levels
IRL3 IRL3 IRL2 IRL2 IRL1 IRL1
IRL3 IRL3 IRL2 IRL2 IRL1 IRL1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no
transient level on the IRL pin change is detected. In standby mode, as the bus clock is stopped,
noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is
not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL interrupt
handling.
Pins IRL0–IRL3 can be used for four independent interrupt requests by setting the IRLM bit to 1
in the ICR register. When independent interrupt requests are used in the SH7750, the interrupt
priority levels are fixed (table 19.4). When independent interrupt requests are used in the
SH7750S or SH7750R, the interrupt priority levels can be set in interrupt priority register D
(IPRD).
Rev. 6.0, 07/02, page 756 of 986
IRL0 IRL0
IRL0 IRL0
Interrupt Priority Level
0 15
1 14
0 13
1 12
0 11
1 10
0 9
1 8
0 7
1 6
0 5
1 4
0 3
1 2
0 1
1 0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request