Hitachi SH7750 Hardware Manual page 70

Table 1.2 Pin Functions (cont)
Pin
No. No. Pin Name
197 C15 VDDQ
198 D15 VSSQ
199 B15 MD7/TXD
200 A16 SCK2/
MRESET
201 C14 VDD
202 D14 VSS
203 A15 A18
204 B14 A19
205 C13 VDDQ
206 D13 VSSQ
207 A14 A20
208 B13 A21
209 A13 A22
210 B12 A23
211 C12 VDDQ
212 D12 VSSQ
213 A12 A24
214 B11 A25
215 A11 MD3/CE2A I/O
216 A10 MD4/CE2B I/O
217 C11 VDDQ
218 D11 VSSQ
219 B10 MD5/RAS2 I/O
220 A9 DACK0
221 B9 DACK1
222 C8 A0
223 C10 VDDQ
224 D10 VSSQ
Rev. 6.0, 07/02, page 20 of 986
I/O Function
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Mode/SCI
data output
I SCIF clock/
manual reset
Power Internal VDD
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Mode/
PCMCIA-CE
Mode/
PCMCIA-CE
Power IO VDD (3.3 V)
Power IO GND (0 V)
Mode/RAS
(DRAM)
O DMAC0 bus
acknowledge
O DMAC1 bus
acknowledge
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
Reset SRAM DRAM
MD7 TXD TXD
MRESET SCK2
SCK2
MD3
MD4
RAS2
MD5
Memory Interface
SDRAM PCMCIA MPX
TXD TXD TXD
SCK2 SCK2 SCK2
CE2A
CE2B