Hitachi SH7750 Hardware Manual page 623

8. Data transfer end request
a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during
channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0,
transfer cannot be ended midway.
b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set
in CHCR0, SAR0, DAR0, and DMATCR0 are retained. With the SH7750, execution
cannot be restarted from an external device in this case. To restart execution in the
SH7750S and SH7750R, set CHCR0.DE = 1 with an MOV instruction.
9. Request queue clearance
a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in
normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are
all cleared. All external requests held on the DMAC side are also cleared.
b. In case 4-d, the DMAC freeze state can be cleared.
c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are
accepted by the DDT in case 11, the DMAC freeze state can be cleared.
10. DBREQ assertion
a. After DBREQ is asserted, do not assert DBREQ again until BAVL is asserted, as this will
result in a discrepancy between the number of DBREQ and BAVL assertions.
b. The BAVL assertion period due to DBREQ assertion is one cycle.
If a row address miss occurs in a read or write in the non-precharged bank during
synchronous DRAM access, BAVL is asserted for a number of cycles in accordance with
the RAS precharge interval set in BSC.MCR.TCP.
c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an
external device. If a row address miss occurs at this time in a read or write in the non-
precharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ
signal asserted by the external device is ignored. Therefore, BAVL is not asserted again
due to this signal.
11. Clearing DDT mode
Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT
bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode,
the DMAC will freeze.
This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT
mode.
12. Confirming DMA transfer requests and number of transfers executed
The channel associated with a DMA bus cycle being executed in response to a DMA transfer
request can be confirmed by determining the level of external pins ID1 and ID0 at the rising
edge of the CKIO clock while TDACK is asserted.
(ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3)
Rev. 6.0, 07/02, page 573 of 986