Hitachi SH7750 Hardware Manual page 746

Sh7750 series superh risc engine
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Start
1
bit
Serial
0
D0
data
RDF
FER
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When
RTS2 is 0, reception is possible.
SH7750:
SH7750S, SH7750R: When RTS2 is 1, this indicates that SCFRDR2 contains a number of
Figure 16.12 shows an example of the operation when modem control is used.
Start
bit
Serial data
0
D0
RxD2
Figure 16.12 Example of Operation Using Modem Control (RTS2
Rev. 6.0, 07/02, page 696 of 986
Data
Parity
Stop
bit
bit
D1
D7
0/1
RXI interrupt
request
One frame
Figure 16.11 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
When RTS2 is 1, this indicates that SCFRDR2 contains 15 or more
bytes of data.
data bytes equal to or greater than the RTS2 output active trigger set
number. The RTS2 output active trigger value is specified by bits 10 to
8 in the FIFO control register (SCFCR2), described in section 16.2.9,
FIFO control register (SCFCR2).
RTS2 also becomes 1 when bit 4 (RE) in SCSCR2 is 0.
Parity
bit
D1 D2
D7 0/1 1
Start
Data
bit
1
0
D0
D1
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
Stop
bit
Parity
Stop
bit
bit
D7
0/1
0
ERI interrupt request
generated by receive
error
Start
bit
0
RTS2)
RTS2
RTS2
0/1

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