Hitachi SH7750 Hardware Manual page 408

• For Synchronous DRAM Interface:
AMX AMXEXT
0 0
1
1 0
1
2 —
3 —
4 —
5 —
6 0
1
0
1
7 —
Notes: *1 a[*]: Not an address pin but an external address
*2 Can only be set in the SH7750R.
*3 Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750).
*4 For details on address multiplexing, refer to appendix F, Synchronous DRAM Address
Multiplexing Tables.
Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is
performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh
request cycle generation timer can be used as an interval timer.
Bit 2: RFSH
0
1
Rev. 6.0, 07/02, page 358 of 986
SZ
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
64
32
32
64
32
Description
Refreshing is not performed
Refreshing is performed
Example of Synchronous DRAM
(16M: 512k × 16 bits × 2) × 4
(16M: 512k × 16 bits × 2) × 2
(16M: 512k × 16 bits × 2) × 4
(16M: 512k × 16 bits × 2) × 2
(16M: 1M × 8 bits × 2) × 8
(16M: 1M × 8 bits × 2) × 4
(16M: 1M × 8 bits × 2) × 8
(16M: 1M × 8 bits × 2) × 4
(64M: 1M × 16 bits × 4) × 4
(64M: 1M × 16 bits × 4) × 2
(64M: 2M × 8 bits × 4) × 8
(64M: 2M × 8 bits × 4) × 4
(64M: 512k × 32 bits × 4) × 2
(64M: 512k × 32 bits × 4) × 1
(64M: 1M × 32 bits × 2) × 2
(64M: 1M × 32 bits × 2) × 1
(128M: 4M × 8 bits × 4) × 8 *
(256M: 4M × 16 bits × 4) × 4 *
(128M: 4M × 8 bits × 4) × 4 *
(256M: 4M × 16 bits × 4) × 2 *
(16M: 256k × 32 bits × 2) × 2
(16M: 256k × 32 bits × 2) × 1
4
BANK *
1
a[22] *
1
a[21] *
1
a[21] *
1
a[20] *
1
a[23] *
1
a[22] *
1
a[22] *
1
a[21] *
1
a[24:23] *
1
a[23:22] *
1
a[25:24] *
1
a[24:23] *
1
a[23:22] *
1
a[22:21] *
1
a[23] *
1
a[22] *
2 1
a[26:25] *
2 1
a[26:25] *
3 1
a[25:24] *
3 1
a[25:24] *
1
a[21] *
1
a[20] *
(Initial value)