Multiple Interrupts; Interrupt Masking With Mai Bit - Hitachi SH7750 Hardware Manual

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Multiple Interrupts

When handling multiple interrupts, interrupt handling should include the following procedures:

1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The

code in INTEVT can be used as a branch-offset for branching to the specific handler.

2. Clear the interrupt source in the corresponding interrupt handler.

3. Save SPC and SSR to the stack.

4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.

5. Handle the interrupt.

6. Set the BL bit in SR to 1.

7. Restore SSR and SPC from memory.

8. Execute the RTE instruction.

When these procedures are followed in order, an interrupt of higher priority than the one being

handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be

shortened for urgent processing.

By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin

is low, irrespective of the BL and IMASK bits in the SR register.

• In normal operation and sleep mode

All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is

generated by a transition at the NMI pin.

• In standby mode

All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a

transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the

MAI bit is set to 1.

Rev. 6.0, 07/02, page 770 of 986

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