Hitachi SH7750 Hardware Manual page 492

Sh7750 series superh risc engine

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In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.

The first access is performed on the data for which there was an access request, and the remaining

accesses are performed on the data at the 32-byte boundary. The bus is not released during this

Figure 13.48 shows the timing when a burst ROM setting is made, and setup/hold is specified in

(SA: IO ← memory)

Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.

2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Rev. 6.0, 07/02, page 442 of 986

Figure 13.46 Burst ROM Basic Access Timing

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