Hitachi SH7750 Hardware Manual page 477

Sh7750 series superh risc engine

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Precharge-sel

(SA: IO → memory)

Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as

shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal

is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn,

and AL (acknowledge level) are 0.

Figure 13.36 Burst Write Timing (Same Row Address)

Single-address DMA

Normal write

Rev. 6.0, 07/02, page 427 of 986

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