Hitachi SH7750 Hardware Manual page 35

Figure 4.8 Memory-Mapped IC Address Array ................................................................ 113
Figure 4.9 Memory-Mapped IC Data Array...................................................................... 114
Figure 4.10 Memory-Mapped OC Address Array .............................................................. 115
Figure 4.11 Memory-Mapped OC Data Array .................................................................... 116
Figure 4.12 Memory-Mapped IC Address Array ................................................................ 118
Figure 4.13 Memory-Mapped IC Data Array...................................................................... 119
Figure 4.14 Memory-Mapped OC Address Array .............................................................. 120
Figure 4.15 Memory-Mapped OC Data Array .................................................................... 121
Figure 4.16 Store Queue Configuration .............................................................................. 122
Figure 5.1 Register Bit Configurations ............................................................................. 128
Figure 5.2 Instruction Execution and Exception Handling ............................................... 133
Figure 5.3 Example of General Exception Acceptance Order .......................................... 134
Figure 6.1 Format of Single-Precision Floating-Point Number ........................................ 161
Figure 6.2 Format of Double-Precision Floating-Point Number....................................... 162
Figure 6.3 Single-Precision NaN Bit Pattern..................................................................... 164
Figure 6.4 Floating-Point Registers................................................................................... 166
Figure 8.1 Basic Pipelines ................................................................................................. 194
Figure 8.2 Instruction Execution Patterns ......................................................................... 195
Figure 8.3 Examples of Pipelined Execution .................................................................... 207
Figure 9.1 STATUS Output in Power-On Reset ............................................................... 237
Figure 9.2 STATUS Output in Manual Reset ................................................................... 237
STATUS Output in Standby → Interrupt Sequence ........................................ 238
Figure 9.3
STATUS Output in Standby → Power-On Reset Sequence ............................ 238
Figure 9.4
STATUS Output in Standby → Manual Reset Sequence ................................ 239
Figure 9.5
STATUS Output in Sleep → Interrupt Sequence ............................................ 240
Figure 9.6
STATUS Output in Sleep → Power-On Reset Sequence ................................ 240
Figure 9.7
STATUS Output in Sleep → Manual Reset Sequence .................................... 241
Figure 9.8
STATUS Output in Deep Sleep → Interrupt Sequence ................................... 242
Figure 9.9
STATUS Output in Deep Sleep → Power-On Reset Sequence....................... 242
Figure 9.10
STATUS Output in Deep Sleep → Manual Reset Sequence ........................... 243
Figure 9.11
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) ... 244
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)....... 245
Figure 9.14 Timing When Power Other than VDD-RTC is Off ......................................... 246
Timing When VDD-RTC Power is Off → On ................................................ 246
Figure 9.15
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) .................................................. 249
Figure 10.1 (2) Block Diagram of CPG (SH7750R)................................................................. 250
Figure 10.2 Block Diagram of WDT................................................................................... 259
Figure 10.3 Writing to WTCNT and WTCSR .................................................................... 263
Figure 10.4 Points for Attention when Using Crystal Resonator ........................................ 265
Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ................................. 266
Figure 11.1 Block Diagram of RTC.................................................................................... 268
Figure 11.2 Examples of Time Setting Procedures ............................................................. 285
Figure 11.3 Examples of Time Reading Procedures ........................................................... 287
Rev. 6.0, 07/02, page xxxv of I