Operation; Endian/Access Size And Data Alignment; Figure 13.5 Writing To Rtcsr, Rtcnt, Rtcor, And Rfcr - Hitachi SH7750 Hardware Manual

15 14
RTCSR,
RTCNT,
1 0
RTCOR
15 14
1 0
RFCR

Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR

Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when
reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0.
13.3

Operation

13.3.1

Endian/Access Size and Data Alignment

The SH7750 Series supports both big-endian mode, in which the most significant byte (MSByte)
is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant
byte (LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a
power-on reset by the RESET pin, big-endian mode being set if the MD5 pin is low, and little-
endian mode if it is high.
A data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for
DRAM, 32 or 64 bits for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data
alignment is carried out according to the data bus width and endian mode of each device. If the
data bus width is smaller than the access size, a number of bus cycles will be generated
automatically until the access size is reached. In this case, address incrementing is performed
automatically according to the bus width as access is performed. For example, if longword access
is performed in an 8-bit bus width area using the SRAM interface, four accesses are executed,
with the address automatically incremented by 1 each time. In 32-byte transfer, a total of 32 bytes
of data are transferred consecutively according to the set bus width. The first access is performed
on the data for which there was an access request, and the remaining accesses are performed on
32-byte boundary data using wraparound. Bus release or refresh operations are not performed
between these transfers. Data alignment and data length conversion between the different
interfaces is performed automatically. Quadword access is used only in transfer by the DMAC.
The relationship between the endian mode, device data length, and access unit, is shown in tables
13.7 to 13.14.
Rev. 6.0, 07/02, page 370 of 986
13 12 11 10
1 0 0 1
13 12 11 10
1 0 0 1
9 8 7 6
0 1
9 8 7 6
Write data
5 4 3 2
Write data
5 4 3 2
1 0
1 0