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13.2.11 Refresh Timer Control/Status Register (RTCSR) ................................................ 364
13.2.12 Refresh Timer Counter (RTCNT)........................................................................ 367
13.2.13 Refresh Time Constant Register (RTCOR) ......................................................... 368
13.2.14 Refresh Count Register (RFCR) .......................................................................... 369
13.2.15 Notes on Accessing Refresh Control Registers.................................................... 369
13.3 Operation .......................................................................................................................... 370
13.3.1 Endian/Access Size and Data Alignment............................................................. 370
13.3.2 Areas .................................................................................................................... 382
13.3.3 SRAM Interface................................................................................................... 387
13.3.4 DRAM Interface .................................................................................................. 395
13.3.5 Synchronous DRAM Interface ............................................................................ 413
13.3.6 Burst ROM Interface............................................................................................ 441
13.3.7 PCMCIA Interface............................................................................................... 444
13.3.8 MPX Interface...................................................................................................... 455
13.3.9 Byte Control SRAM Interface ............................................................................. 473
13.3.10 Waits between Access Cycles.............................................................................. 478
13.3.11 Bus Arbitration .................................................................................................... 480
13.3.12 Master Mode ........................................................................................................ 483
13.3.13 Slave Mode .......................................................................................................... 484
13.3.14 Partial-Sharing Master Mode............................................................................... 485
13.3.15 Cooperation between Master and Slave............................................................... 486
13.3.16 Notes on Usage .................................................................................................... 487
14.1 Overview........................................................................................................................... 489
14.1.1 Features................................................................................................................ 489
14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 492
14.1.3 Pin Configuration (SH7750, SH7750S)............................................................... 493
14.1.4 Register Configuration (SH7750, SH7750S)....................................................... 494
14.2 Register Descriptions (SH7750, SH7750S) ...................................................................... 496
14.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... 496
14.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3).................................. 497
14.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)......................... 498
14.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... 499
14.2.5 DMA Operation Register (DMAOR)................................................................... 507
14.3 Operation .......................................................................................................................... 510
14.3.1 DMA Transfer Procedure .................................................................................... 510
14.3.2 DMA Transfer Requests ...................................................................................... 512
14.3.3 Channel Priorities ................................................................................................ 515
14.3.4 Types of DMA Transfer....................................................................................... 518
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 527
14.3.6 Ending DMA Transfer ......................................................................................... 541
14.4 Examples of Use ............................................................................................................... 544
Rev. 6.0, 07/02, page xxviii of I
.......................................... 489
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