H-Udi Reset; H-Udi Interrupt - Hitachi SH7750 Hardware Manual

21.3.2

H-UDI Reset

A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset
assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see
figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset
negate command is the same as the length of time the reset pin is held low in order to effect a
power-on reset.
H-UDI
H-UDI
H-UDI pin
reset negate
reset assert
Chip internal reset
CPU state
Normal Reset Reset processing
Figure 21.3 H-UDI Reset
21.3.3

H-UDI Interrupt

The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the
H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an
address based on VBR and return effected by means of an RTE instruction. The exception code
stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be
controlled with bits 3 to 0 of control register IPRC.
In the SH7750 or SH7750S, the H-UDI interrupt request signal is asserted for about eight cycles
of the LSI's on-chip peripheral clock after the command is set. The number of cycles for assertion
is determined by the ratio of TCK to the frequency of the on-chip peripheral clock. Since the
period of assertion is limited, the CPU may miss a request.
In the SH7750R, the H-UDI interrupt request signal is asserted when the INTREQ bit in the
SDINT register is set to 1 after the command is set (Update-IR). The interrupt request signal will
not be negated unless a 0 is written to the INTREQ bit by software; therefore, the CPU will not
miss a request. As long as the H-UDI interrupt command is set in SDIR, the SDINT register is
connected between the TDI and TDO pins.
Note that, in the SH7750 or SH7750S, the H-UDI interrupt command automatically becomes a
bypass command immediately after it has been set. In the SH7750R, the command is not changed
except by the following operations: update in the Update-IR state, initialization in the Test-Logic-
Reset state, and initialization by assertion of TRST.
Rev. 6.0, 07/02, page 811 of 986