Hd6417750Svbt133: V - Hitachi SH7750 Hardware Manual

Table 22.32 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133)

HD6417750SVBT133: V

HD6417750SVF133: V
Item
EXTAL PLL2
clock input operating
frequency
PLL2 not
operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width t
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
RESET assert time
PLL synchronization settling time
Rev. 6.0, 07/02, page 858 of 986
= 3.0 to 3.6 V, V
DDQ DD
= 3.0 to 3.6 V, V
DDQ DD
Symbol
1/2 divider f
EX
operating
1/2 divider not f
EX
operating
1/2 divider f
EX
operating
1/2 divider not f
EX
operating
t
EXcyc
t
EXL
EXH
t
EXr
t
EXf
f
OP
f
OP
t
cyc
t
CKOL1
t
CKOH1
t
CKOr
t
CKOf
t
CKOL2
t
CKOH2
t
OSC1
t
OSCMD
t
SCK2RS
t
SCK2RH
t
MDRS
t
MDRH
t
RESW
t
PLL
= 1.5 V typ, T = –30 to +70°C, C
a
= 1.5 V, T = –20 to +75°C, C
a
Min Max
16 45
8 23
2 45
1 23
22 1000
3.5 —
3.5 —
— 4
— 4
25 67
1 67
14 1000
1 —
1 —
— 3
— 3
3 —
3 —
10 —
10 —
20 —
20 —
3 —
20 —
20 —
200 —
= 30 pF
L
= 30 pF
L
Unit Figure
MHz
ns 22.1
ns 22.1
ns 22.1
ns 22.1
ns 22.1
MHz
MHz
ns 22.2(1)
ns 22.2(1)
ns 22.2(1)
ns 22.2(1)
ns 22.2(1)
ns 22.2(2)
ns 22.2(2)
ms 22.3, 22.5
ms 22.3, 22.5
ns 22.11
ns 22.3, 22.5, 22.11
t 22.12
cyc
ns 22.3, 22.5, 22.12
t 22.3, 22.4, 22.5,
cyc
22.6, 22.11
µs
22.9, 22.10