Hitachi SH7750 Hardware Manual page 691

Sh7750 series superh risc engine
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Figure 15.16 shows an example of SCI operation for multiprocessor format reception.
Start
1
Data (ID1)
bit
Serial
0
D0
D1
data
MPIE
RDRF
SCRDR1
value
RXI interrupt request
(multiprocessor
interrupt)
MPIE = 0
Start
1
Data (ID2)
bit
Serial
0
D0
D1
data
MPIE
RDRF
SCRDR1
ID1
value
RXI interrupt request
(multiprocessor interrupt)
MPIE = 0
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Stop
Start
MPB
bit
bit
D7
1
1
0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
(a) Data does not match station's ID
Stop
Start
MPB
bit
bit
D7
1
1
0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
(b) Data matches station's ID
Bit, One Stop Bit)
Data
MPB
(Data1)
D0
D1
D7
0
ID1
As data is not this
RXI interrupt
station's ID, MPIE
request
bit is set to 1 again
Data
MPB
(Data2)
D0
D1
D7
0
ID2
As data matches this
station's ID, reception
continues and data is
received by RXI
interrupt handler
Rev. 6.0, 07/02, page 641 of 986
Stop
1
bit
Idle state
1
(mark state)
The RDRF flag
is cleared to 0
by the RXI
interrupt handler.
Stop
1
bit
Idle state
1
(mark state)
Data2
MPIE bit set
to 1 again

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