Figure 22.34 Synchronous Dram Bus Cycle: Synchronous Dram Auto-Refresh (Tras = 1, Trc[2:0] = 001) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Precharge-sel

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh

Rev. 6.0, 07/02, page 896 of 986

(TRAS = 1, TRC[2:0] = 001)

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