Figure 22.30 Synchronous Dram Normal Write Bus Cycle: Act + Write Commands, Burst (Rcd[1:0] = 01, Trwl[2:0] = 010) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Precharge-sel

(SA: IO → memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,

Rev. 6.0, 07/02, page 892 of 986

Burst (RCD[1:0] = 01, TRWL[2:0] = 010)

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