CKIO
BANK
Precharge-sel
Address
RD/
DQMn
t
D63–D0
(write)
CKE
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
Rev. 6.0, 07/02, page 890 of 986
Tr
Trw
Tc1
t
AD
Row
t
AD
Row
H/L
Column
Row
t
CSD
t
RWD
t
t
RASD
RASD
t
CASD2
t
CASD2
t
DQMD
WDD
t
WDD
c0
t
BSD
t
t
DACD
DACD
(RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
Tc2
Tc3
Tc4
t
RWD
t
CASD2
t
DQMD
t
WDD
t
BSD
Trwl
Trwl
Tpc
t
AD
t
CSD