Hitachi SH7750 Hardware Manual page 11

Section
13.2.8 Memory Control
Register (MCR)
13.2.10 Synchronous DRAM
Mode Register (SDMR)
13.3.1 Endian/Access Size
and Data Alignment
13.3.2 Areas
13.3.3 SRAM Interface
13.3.4 DRAM Interface
13.3.5 Synchronous DRAM
Interface
13.3.6 Burst ROM Interface
Page Item
355 Bits 15 to 13—Write
Precharge Delay (TRWL2–
TRWL0)
358 For Synchronous DRAM
Interface
362 to
364
370
371 Data Configuration
382 Area 0, Area 1
387
387 Basic Timing
388, 393 Figures 13.6, 13.11 to 13.13
to 395
395 Read-Strobe Negate Timing
(Setting Only Possible in the
SH7750R)
400 to 408 Figures 13.17 to 13.22
413 Connection of Synchronous
DRAM
415 Address Multiplexing
417 to Figure 13.28 to 13.37
428
435 Power-On Sequence
438 Notes on Changing the Burst
Length (Variation Only
Possible in the SH7750R)
440 Connecting a 128-Mbit/256-
Mbit Synchronous DRAM with
64-bit Bus Width
441, 442
442 to 444 Figure 13.46 to 13.48
Description
Description added
AMX6 description and
Notes amended
Description amended,
and Note added
Description amended
Quadword partially
amended
Description added and
amended
Basic interface changed
to SRAM interface
Description amended
Notes added
Description added and
amended
Notes added
Description added
Description amended
Note added
Newly added
Newly added
Newly added
Description amended
Notes added
Rev. 6.0, 07/02, page xi of I